This invention relates to a communication apparatus, a communication method and a storage medium. More particularly, it relates to a communication apparatus, a communication method and a storage medium for transmitting and receiving digital audio data and video data, utilizing ATM communication technique.
FIG. 1 illustrates the structure of a conventional data communication system. The network 3 that connects the encoding side and the decoding side is assumed to be using a satellite as in the transmission method employed in digital CS broadcasting. In other words, it is assumed that the data transmitted via the network 3 is delayed at regular intervals.
The encoder 1 encodes, for example, video data and audio data, as the data to be transmitted, in accordance with the MPEG-2 system and outputs the encoded data to the system encoder 2. The system encoder 2 encodes the input video and audio data, generating a transport stream packet. If necessary, the system encoder 2 multiplexes the transport stream packet with another transport stream packet and outputs them onto the network 3.
The system encoder 2 incorporates PCR (Program Clock Reference), i.e., a time stamp, into the header of the transport stream packet generated, as is shown in FIG. 2. (Hereinafter, the transport stream packet into which the PCR has been incorporated shall be called xe2x80x9cPCR packetxe2x80x9d.) The PCR is a count value of the system clock C1 (a clock having frequency of 27 MHz in the case of the MPEG-2 system) which has been counted at the timing of outputting the transport stream from the encoding side. The PCR is incorporated into the transport stream so that at least one may be output within 0.1 second from the encoding side in accordance with the MPEG-2 system standards.
Referring back to FIG. 1, the transport stream packet (including the PCR packet) is transmitted through the network 3, reaches the decoding side and input to the system decoder 4 provided in the decoding side. The data transmitted via the network 3 is delayed by a predetermined time. The PCR (PCR packet) therefore reaches the decoding side in the same interval as the interval at which it has been transmitted from the encoding side. (The difference should fall within +/xe2x88x92500 ns.)
The system decoder 4 de-packetizes the input transport stream packet, generating an audio stream or a video stream, which is output to the decoder 5. The system decoder 4 extracts the PCR from the PCR packet as is illustrated in FIG. 2. The decoder 4 compares the PCR with the count value of the system clock C2 (a clock signal having frequency of 27 MHz) in the decoding side, which has been obtained at the timing of extracting the PCR. The decoder 4 adjusts the speed of the system clock C2 based on the results of comparison, and supplies the system clock C2 to the decoder 5.
The decoder 5 decodes the audio data or video data supplied from the system decoder 4, in synchronism with the system clock C2 supplied from the system decoder 4.
How the system clock C2 is generated (adjusted) in the decoding side will be now be described, with reference to FIGS. 3 and 4. The system decoder 4 has the structure shown in FIG. 3. The transport stream packet supplied to the system decoder 4 is supplied to the system decoder 11 and time stamp extracting circuit 12 of the system decoder 4.
As shown in FIG. 2, the time stamp extracting circuit 12 extracts the PCR incorporated in the PCR packet and supplies the PCR to a PLL circuit 13. The PLL circuit 13 has, for example, the structure shown in FIG. 4. It has a subtracter 21, to which the PCR extracted by the time stamp extracting circuit is input. Also input to the subtracter 21 is the count value of a counter 24 when the PCR is input. The count value is a count of the number of clock pulses output from a VCO (Voltage-Controlled Oscillator) 23. The subtracter 21 finds the difference between the PCR and the count value, which have been supplied from the time stamp extracting circuit 12 and the counter 24, respectively. A low-pass filter (hereinafter referred to as xe2x80x9cLPFxe2x80x9d) 22 smoothes, with time, the result of the subtraction supplied from the subtracter 21 and outputs the same to the VCO 23. The VCO 23, which also functions as a D/A converter, then converts the digital signal input from the LPF 22 to an analog signal. Using the analog signal as a control voltage, the VCO generates a system clock C2 having a frequency corresponding to the control voltage. The VCO 23 then outputs the system clock to the counter 24 and the decoder 5.
The counter 24 counts the pulses of the system clock C2 supplied from the VCO 23 acting as a D/A converter. The count value of the counter 24 is supplied to the substracter 21 as the signal that indicates the frequency and phase that the system clock C2 has at this time. That is, the PLL circuit 13 adjust the speed of the system clock C2 so that the difference between the PCR value incorporated in the transport stream packet and the count value of the system clock C2, obtained when the PCR was extracted (when the PCR packet reaches the decoding side) may be eliminated. As a result, the system clock C2 in the decoding side becomes synchronous with the system clock C1 in the encoding side.
With reference to FIG. 3 again, the system decoder 11 de-packetizes the input transport stream packet, generating an audio stream and a video stream. The audio stream and video stream are output to the decoder 5.
A satellite may be used as the network 3 as in the transmission method employed in satellite broadcasting. In this case, a fixed delay is added to the transport stream packet transmitted from the encoding side. That is, the transport stream packet transmitted from the encoding side reaches the decoding side, earlier or later by a specific time. Since the specific time is constant, the interval at which the transport stream packet (including the PCR packet) reaches the decoding side is the same as the interval at which it is output from the encoding side. Thus, the system clock C2 in the decoding side is generated, synchronous with the system clock Cl in the encoding side, by the method explained with reference to FIGS. 3 and 4.
If the network 3 is an ATM (Asynchronous Transfer Mode) network, however, the transport stream packet transmitted from the encoding side is delayed, not at a constant interval but at an interval fluctuating in the range of 1 ms to 2 ms (hereinafter referred to as xe2x80x9cdelay fluctuationxe2x80x9d) . The delay fluctuation cannot be absorbed in the data transmission system described above. After all, the delay greatly exceeds the MPEG-2 standard range of +/xe2x88x92500 ns. In consequence, the data cannot be reproduced adequately.
A synchronization method, such as adaptive clock method, has been proposed. In the method, the delay fluctuation is first attenuated to some extent and a system clock is then generated.
FIG. 5 shows an example of the adaptive clock circuit 51 which is provided in the decoding side and which uses the adaptive clock method. It is assumed here that delay fluctuation exists in the data transmitted via a network 50.
The data with delay fluctuation, transmitted via the network 50, is input to the FIFO 52 incorporated in the adaptive clock circuit 51. The FIFO 52 holes the data for some time and outputs the data in response to a read clock supplied from a control circuit 53. The FIFO 52 outputs a signal to an LPF 54. The signal represents the data occupation ratio of the FIFO 52. The LPF 54 smoothes the data occupation ratio and outputs the same to the control circuit 53.
The control circuit 53 controls the speed of a read clock to be output to the FIFO 52, so that the data supplied from the LPF 54 (i.e., the smoothed data occupation ratio of the FIFO 52) may have a prescribed value. That is, the clock controlled by the control circuit 53 is used as system clock in the decoding side.
In the adaptive clock system, the system clock for the decoding side is generated from the received data only. The apparatus can therefore be simple in structure. In this example, however, the jitter component is shaped in analog fashion. Inevitably, the jitter component remains for a long time, and the delay fluctuation cannot be adequately absorbed.
A data communication system has been proposed, which comprises a transmission apparatus 61 shown in FIG. 6 and a receiving apparatus 62 shown in FIG. 7. The system is designed for use in, for example, television broadcast stations or program producing companies, to transmit a plurality of programs synchronized with the clocks used in the stations and companies.
As shown in FIG. 6, the transmission apparatus 61 has a PLL circuit 71 and N synchronous data generating circuits 72-1 to 72-N (hereinafter, collectively referred to as xe2x80x9csynchronous data generating section 72xe2x80x9d so far as they need not be distinguished from one another, and other components will be similarly referred to). The PLL circuit 71 receives an 8 HKz clock, i.e., the network clock for the network 63. The PLL circuit 71 has a phase comparator 91, the structure of which is illustrated in FIG. 8. The phase comparator 91 has a VCO 92 and a frequency divider 93. The VCO 92 generates a 27 MHz signal having a predetermined phase. The signal is supplied to the frequency divider 93 and to the synchronous data generating circuits 72-1 to 72-N.
The frequency divider 93 divides the frequency of the 27 MHz clock input from the VCO 92 with a division ratio of 1/3375, generating an 8 KHz clock. The 8 KHz clock is output to a phase comparator 94. The phase comparator 94 compares the 8 KHz clock and the 8 KHz clock supplied from the network 63 and frequency divider 93, respectively, in terms of phase, and outputs the result of the comparison to the VCO 92.
The synchronous data generating circuit 72-1 comprises a PLL circuit 81, a latch circuit 82, a clock 83 and the like. The PLL circuit 81 receives, for example, the time stamp contained in the data generated in synchronism with a prescribed clock. The PLL circuit 81 is the same in structure as the PLL circuit 13 shown in FIG. 4. That is, the PLL circuit 81 generates a prescribed clock from the input time stamp and outputs the clock to the latch circuit 82.
The latch circuit 82 performs a latching process in accordance with the clock supplied from the PLL circuit 81 and the clock signal supplied from the clock 83. The data reproduced from the result of the latching process is synchronous data, which is incorporated into a predetermined transport stream packet.
The synchronous data generating circuits 72-2 to 72-N have the same structure as the synchronous data generating circuit 72-1. Their structure will not be illustrated or described in detail. They receive the time stamps contained in data items generated in synchronism with different clocks, and generate data items synchronous with the clocks, respectively.
As shown in FIG. 7, the receiving apparatus 62 comprises a PLL circuit 101 and N system clock regenerating circuits 102-1 to 102-N. The PLL circuit 101 receives an 8 KHz clock, which is the network clock of the network 63. Like the PLL circuit 71 of the transmission apparatus 61, the PLL circuit 101 generates a 27 MHz clock that corresponds to the 8 KHz clock input. The 27 MHz clock is output to the system clock regenerating circuits 102-1 to 102-N.
The system clock regenerating circuit 102-1 comprises a clock 110, a PLL circuit 111 and the like. The clock 110 of the system clock regenerating circuit 102-1 receives the clock supplied from the PLL circuit O1. The clock 110 divides the frequency of the clock with a division ratio of 1/27000000, generating a clock signal. The clock signal is output to the PLL circuit 111. The PLL circuit 111 receives the clock from the clock 110 and the synchronous data generated by the synchronous data generating circuit 72-1 of the transmission apparatus 61. The PLL circuit 111 regenerates the system clock from the clock and synchronous data that have been input to it.
The system clock regenerating circuits 102-2 to 102-N have the same structure as the system clock regenerating circuit 102-1. Therefore, they will not be shown in detail. They regenerate system clocks from the synchronous data items supplied from the corresponding synchronous data generating circuits 72. The system clocks, thus regenerated, are synchronous with the clocks used to encode the respective data items. Data can therefore be appropriately reproduced by decoding the data by using the respective clocks.
The data transmission system described above, however, needs to have a synchronous data generating circuit 72 and a system clock regenerating circuit 102 for each of the clocks which are used to encode the input data. The apparatus would inevitably be complicated and large.
In the present invention, a time stamp added to input data is read. The count value of the network clock is held at the time the data is input. A reference clock value is determined from the time stamp read and the count value of the network clock at the time the data including the time stamp is input. An error of the time stamp of the data when the time stamp is isolated from the reference clock value by a fixed clock is calculated from the distance between the reference clock value and the time stamp read and the distance that exists between the reference clock value and the count value of the network clock when the data held and containing the time stamp is input. The error calculated by the calculating means is written. The data containing the time stamp that includes the error is transmitted to the receiving apparatus.
That is, a communication apparatus according to the present invention is characterized by comprising: reading means for reading a time stamp added to input data; holding means for holding a count value of the network clock at the time the data is input; determining means for determining a reference clock value from the time stamp read by the reading means and the count value of the network clock, held by the holding means, at the time the data including the time stamp is input; calculating means for calculating an error of the time stamp of the data when the time stamp is isolated from the reference clock value by a fixed clock, from the distance between the reference clock value and the time stamp read by the reading means and the distance that exists between the reference clock value and the count value of the network clock when the data held by the holding means and containing the time stamp is input; writing means for writing the error calculated by the calculating means; and transmitting means for transmitting, to the receiving apparatus, the data containing the time stamp that includes the error written by the writing means.
A communication method according to the invention is characterized by comprising: a reading step of reading a time stamp added to input data; a holding step of holding a count value of the network clock at the time the data is input; a determining step of determining a reference clock value from the time stamp read by the reading means and the count value of the network clock, held by the holding means, at the time the data including the time stamp is input; a calculating step of calculating an error of the time stamp of the data when the time stamp is isolated from the reference clock value by a fixed clock, from the distance between the reference clock value and the time stamp read by the reading means and the distance that exists between the reference clock value and the count value of the network clock when the data held by the holding means and containing the time stamp is input; a writing step of writing the error calculated by the calculating means; and a transmitting step of transmitting, to the receiving apparatus, the data containing the time stamp that includes the error written by the writing means.
A recording medium according to the invention records a program which describes: a reading step of reading a time stamp added to input data; a holding step of holding a count value of the network clock at the time the data is input; a determining step of determining a reference clock value from the time stamp read by the reading means and the count value of the network clock, held by the holding means, at the time the data including the time stamp is input; a calculating step of calculating an error of the time stamp of the data when the time stamp is isolated from the reference clock value by a fixed clock, from the distance between the reference clock value and the time stamp read by the reading means and the distance that exists between the reference clock value and the count value of the network clock when the data held by the holding means and containing the time stamp is input; a writing step of writing the error calculated by the calculating means; and a transmitting step of transmitting, to the receiving apparatus, the data containing the time stamp that includes the error written by the writing means.
According to this invention, a time stamp added to input data is read. Error information contained in the input data and corresponding to a predetermined fixed clock is read. A count value of the network clock is held at the time the data is input. A reference clock value is determined from the time stamp read, and the count value of the network clock, held by the holding means, at the time the data held and including the time stamp is input. An offset value is determined from the time stamp read and from the count value of the network clock held and acquired at the time the data containing the time stamp is input. The time stamp is updated on the basis of the time stamp read, the error information written to the data containing the time stamp, the reference clock value determined, the offset value determined and the fixed clock.
That is, a communication apparatus according to the present invention is characterized by comprising: first reading means for reading a time stamp added to input data; second reading means for reading error information contained in the input data and corresponding to a predetermined fixed clock; holding means for holding a count value of the network clock at the time the data is input; first determining means for determining a reference clock value from the time stamp read by the first reading means and the count value of the network clock, held by the holding means, at the time the data held by the holding means and including the time stamp is input; second determining means for determining an offset value from the time stamp read by the first reading means and from the count value of the network clock held by the holding means and acquired at the time the data containing the time stamp is input; and updating means for updating the time stamp on the basis of the time stamp read by the first reading means, the error information written to the data containing the time stamp, the reference clock value determined by the first determining means, the offset value determined by the second determining mans and the fixed clock.
A communication method according to the invention is characterized by comprising: a first reading step of reading a time stamp added to input data; a second reading step of reading error information contained in the input data and corresponding to a predetermined fixed clock; a holding step of holding a count value of the network clock at the time the data is input; a first determining step of determining a reference clock value from the time stamp read by the first reading means and the count value of the network clock, held by the holding means, at the time the data held by the holding means and including the time stamp is input; a second determining step of determining an offset value from the time stamp read by the first reading means and from the count value of the network clock held by the holding means and acquired at the time the data containing the time stamp is input; and an updating step of updating the time stamp on the basis of the time stamp read by the first reading means, the error information written to the data containing the time stamp, the reference clock value determined by the first determining means, the offset value determined by the second determining mans and the fixed clock.
A recording medium according to the invention records a program which describes: a first reading step of reading a time stamp added to input data; a second reading step of reading error information contained in the input data and corresponding to a predetermined fixed clock; a holding step of holding a count value of the network clock at the time the data is input; a first determining step of determining a reference clock value from the time stamp read by the first reading means and the count value of the network clock, held by the holding means, at the time the data held by the holding means and including the time stamp is input; a second determining step of determining an offset value from the time stamp read by the first reading means and from the count value of the network clock held by the holding means and acquired at the time the data containing the time stamp is input; and an updating step of updating the time stamp on the basis of the time stamp read by the first reading means, the error information written to the data containing the time stamp, the reference clock value determined by the first determining means, the offset value determined by the second determining mans and the fixed clock.